When fabricating integrated circuits, layers of insulating, conducting and semiconducting materials are deposited and patterned to produce desired structures. “Back end” or metallization processes include contact formation and metal line or wire formation. Contact formation vertically connects conductive layers through an insulating layer. Conventionally, contact vias or openings are formed in the insulating layer, which typically comprises a form of oxide such as borophosphosilicate glass (BPSG) or oxides formed from tetraethylorthosilicate (TEOS) precursors. The vias are then filled with conductive material, thereby interconnecting electrical devices and wiring above and below the insulating layers. The layers interconnected by vertical contacts typically include horizontal metal lines running across the integrated circuit. Such lines are conventionally formed by depositing a metal layer over the insulating layer, masking the metal layer in a desired wiring pattern, and etching away metal between the desired wires or conductive lines.
Damascene processing involves forming trenches in the pattern of the desired lines, filling the trenches with a metal or other conductive material, and then etching the metal back to the insulating layer. Wires are thus left within the trenches, isolated from one another in the desired pattern. The etch back process thus avoids more difficult photolithographic mask and etching processes of conventional metal line definition, particularly for copper metallization.
In an extension of damascene processing, a process known as dual damascene involves forming two insulating layers, typically separated by an etch stop material, and forming trenches in the upper insulating layer, as described above for damascene processing. Contact vias are etched through the floor of the trenches and the lower insulating layer to expose lower conductive elements where contacts are desired. As one of skill in the art will recognize, a number of processes are available for forming dual damascene structures. For example, trenches may be etched through the upper insulating layer, after which a further mask is employed to etch the contact vias or the etch continues through a previously defined, buried hard mask. In an alternative embodiment, contact vias are first etched through the upper and lower insulating layers, after which the via in the upper insulating layer is widened to form a trench.
Protective barriers are often formed between via or trench walls and metals in a substrate assembly, to aid in confining deposited material within the via or trench walls.
These lined vias or trenches are then filled with metal by any of a variety of processes, including chemical vapor deposition (CVD), physical vapor deposition (PVD), and electroplating.
FIG. 1 illustrates a self-aligned dual damascene process in which an upper insulating layer 10 is formed over a lower insulating layer 12, which is in turn formed over a conductive wiring layer 14, preferably with an intervening barrier layer 15. This barrier layer 15 serves to reduce or prevent diffusion of copper or other conductive material from the underlying runner 14 into the overlying dielectric layer 12 and also serves as an etch stop during via formation.
A mask is employed to pattern and etch trenches 16 and contact vias 20 in a desired wiring pattern. In the illustrated embodiment, the trench 16 is etched down to the level of an etch stop layer 19, which is formed between the two insulating layers 10, 12. In the self-aligned dual damascene process this etch stop layer 19 is typically patterned and etched prior to deposition of the upper insulating layer 10 to form a buried hard mask that defines horizontal dimensions of desired contact vias that are to extend from the bottom of the trench 16. Continued etching through the hard mask 19 opens a contact via 20 from the bottom of the trench 16 to the lower conductive wiring layer 14. FIG. 1 also shows an upper etch stop or chemical mechanical polishing (CMP) stop layer 21 over the upper insulating layer 10 to stop a later planarization step, as will be appreciated by the skilled artisan.
As described briefly above, the etch stop layers in damascene processing typically act as a stop layer during dry-etch or CMP process steps. These stop layers are typically deposited by plasma enhanced CVD (PECVD). While etch stop layers have traditionally been silicon nitride, particularly Si3N4, more recently silicon carbide (SiC) and silicon oxycarbide (SiOC) have been employed. Some hydrogen may also be incorporated into the etch stop layer during deposition. In acting as a stop layer, the etch stop prevents wear of the underlying insulation material and/or copper layers by an etch or CMP process. Further, an etch stop layer may serve as a diffusion barrier, preventing copper diffusion from copper lines into the insulation layers.
The inventors have found that current deposition of SiC etch stop layers on copper can result in pinholes, higher leakage currents and/or adhesion problems. This can lead to enhanced diffusion of copper into the insulating layer and may result in lower resistance during dry-etch and CMP processes. This, in turn, may lead to loss of etch-selectivity and reduced adhesion of the deposited layers.
Accordingly, a need exists for more effective methods of depositing etch stop layers, particularly in the context of dual damascene metallization.